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A-Data
Synchronous DRAM General Description
The ADS7608A4A are four-bank Synchronous DRAMs organized as 4,194,304 words x 8 bits x 4 banks. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications
ADS7608A4A
4M x 8 Bit x 4 Banks Features
*JEDEC standard LVTTL 3.3V power supply *MRS Cycle with address key programs -CAS Latency (2 & 3) -Burst Length (1,2,3,8,& full page) -Burst Type (sequential & Interleave) *4 banks operation *All inputs are sampled at the positive edge of the system clock *Burst Read single write operation *Auto & Self refresh *4096 refresh cycle *DQM for masking *Package:54-pins 400 mil TSOP-Type II
Ordering Information.
Part No. ADS7608A4A-5 ADS7608A4A-55 ADS7608A4A-6 ADS7608A4A-7 ADS7608A4A-7.5 Frequency 200Mhz 183Mhz 166Mhz 143Mhz 133Mhz Interface LVTTL LVTTL LVTTL LVTTL LVTTL Package 400mil 54pin TSOPII 400mil 54pin TSOPII 400mil 54pin TSOPII 400mil 54pin TSOPII 400mil 54pin TSOPII
Pin Assignment
VDD DQ0 VDDQ NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ NC VDD NC /WE /CAS /RAS /CS BA0 BA1 A10/AP A0 A1 A2 A3 VDD
1 2 3
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
54
53
52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
Vss DQ7 VssQ NC DQ6 VDDQ NC DQ5 VSSQ NC DQ4 VDDQ NC VSS NC/RFU DQM CK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS
54-pin plastic TSOP II 400 mil
Rev 1 April, 2001
1
A-Data
Pin Description
PIN CK CKE NAME System Clock Clock Enable FUNCTION Active on the positive edge to sample all inputs.
ADS7608A4A
Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least on cycle prior new command. Disable input buffers for power down in standby
/CS
Chip Select
Disables or Enables device operation by masking or enabling all input except CK, CKE and L(U)DQM
A0~A11
Address
Row / Column address are multiplexed on the same pins. Row address : RA0~RA11 Column address : CA0~CA9
BA0~BA1 Banks Select
Selects bank to be activated during row address latch time. Selects bank for read / write during column address latch time.
DQ0~DQ7 Data L(U)DQM Data Mask /RAS /CAS /WE Row Address Strobe Column Address Strobe Write Enable
Data inputs / outputs are multiplexed on the same pins. Makes data output Hi-Z, Latches row addresses on the positive edge of the CLK with /RAS low Latches Column addresses on the positive edge of the CLK with /CAS low Enables write operation and row recharge. Power and Ground for the input buffers and the core logic. Power supply for output buffers. This pin is recommended to be left No Connection on the device.
VDD/VSS Power Supply/Ground VDDQ/VSSQ Data Output Power/Ground NC No Connection
Block Diagram
CK CKE Address
Clock Generator
Bank3 Bank2 Bank1
Row Decoder
Mode Register
Address Buffer & Refresh Counter
Bank0
Amplifier
Command Decoder
/RAS /CAS /WE
Control Logic
/CS
Data Latch
Column Address Buffer & Refresh Counter
Column Decoder
DQM DQS
Data Control Circuit
DQ0~DQn
Rev 1 April, 2001
2
A-Data
Absolute Maximum Ratings
Parameter Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Storage temperature Power dissipation Short circuit current Symbol VIN, Vout VDD, VDDQ TSTG PD IOS Value -1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ +150 1 50
ADS7608A4A
Unit V V W mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC Operating Condition
Voltage referenced to Vss = 0V, TA = 0 to 70 Parameter Supply voltage Input logic high voltage Input logic low voltage Output logic high voltage Output logic low voltage Input leakage current Output leakage current Symbol VDD, VDDQ VIH VIL VOH VOL IIL IOL Min 3.0 2.0 -0.3 2.4 -5 -5 Typ 3.3 3.0 0 Max 3.6 VDD+0.3 0.8 0.4 5 5 Unit V V V V V uA uA 1 2 IOH=-2mA IOL=2mA 3 4 Note
Note : 1. VIH (max)=4.6V AC for pulse width 10ns acceptable. 2.VIL(min)=-1.5V AC for pulse width 10ns acceptable. 3.Any input 0V VIN VDD + 0.3V, all other pins are not under test = 0V. 4.Dout is disabled, 0V VOUT VDD.
AC Operating Condition
Voltage referenced to Vss = 0V, TA = 0 to 70 Parameter AC input high / low level voltage Input timing measurement reference level voltage Input rise / fall time Output timing measurement reference level Output load capacitance for access time measurement Note: 1. 3.15V VDD 3.6V is applied for ADS7608A4A5. Symbol VIH / VIL Vtrip TR / tF Voutfef CL Value 2.4 / 0.4 1.4 1 1.4 50 Unit V V Ns V pF 2 Note
2. Output load to measure access times is equivalent to two TTL gates and one capacitor (30pF). For details, refer to AC/DC output load circuit.
Rev 1 April, 2001
3
A-Data
Capacitance
TA=25, f-=1Mhz, VDD=3.3V Parameter Input capacitance CLK A0~A11,BA0,BA1,CKE,/CS,/RAS, /CAS,/WE,DQM Data input / output capacitance DQM CI/O 4 Pin Symbol Cl1 Cl2 Min 2.5 2.5
ADS7608A4A
Max 4 5
Unit pF pF
6.5
pF
Output load circuit
3.3 V
1200 ohms VOH(DC) = 2.4V,IOH= -2mA VOL(DC) = 0.4V,IOL= 2mA
50 pF 870 ohms
Output
DC Characteristics I
Parameter Input leakage current Output leakage current Output high voltage Output low voltage ILI ILO VOH VOL Symbol Min -1 -1 2.4 Max 1 1 0.4 Unit uA uA V V Note 1 2 IOH = -4mA IOL = 4mA
Note : 1.VIN = 0 TO 3.6V, All other pins are not tested under VIN = 0V. 2.DOUT is disabled, VOUT = 0 to 3.6.
Rev 1 April, 2001
4
A-Data
DC Characteristics II
Speed Parameter Symbol Test condition -5 Burst length=1, One bank active Operating Current Precharge standby current in power down mode IDD2PS CKEVIL(max), tCK= CKEVIH(min), /CSVIH(min), tCK=min input signals are Precharge standby current in Non power down mode IDD2NS Input signals are stable. Active standby current in power down mode IDD3PS CKEVIL(max), tCK= CKEVIH(min), /CSVIH(min), tCK=min input signals are Active standby current in Non power down mode IDD3NS Input signals are stable. Burst mode operating IDD4 current Auto refresh current Self refresh current IDD5 active IDD6 CKE0.2V 1 All banks active tRRCtRRC(min), All banks 160 tCKtCK(min),IOL=0 mA 160 160 155 150 IDD3N changed one time during 2clks. All other pins VDD-0.2V or 0.2V CKEVIH(min), tCK= 20 30 5 IDD3P CKEVIL(max), tCK=min 6 IDD2N changed one time during 2clks. All other pins VDD-0.2V or 0.2V CKEVIH(min), tCK= 12 15 2 IDD1 tRCtRC(min),IOL=0mA CKEVIL(max), tCK=min 115 113 110 105 -5.5 -6 -7
ADS7608A4A
Unit -7.5 100 mA
Note
1
IDD2P
2 mA
mA
mA
mA
150
mA
1
mA mA
2
Note: 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open. 2. Min. of tRRC is shown at AC characteristics.
Rev 1 April, 2001
5
A-Data
AC Characteristics
-5 Parameter System clock /CAS Latency = 3 Cycle time /CAS Latency = 2 Symbol Min tCK3 tCK2 tCHW tCLW tAC3 tAC2 tRC tRRC tRCD tRAS tRP tRRD tCCD 5 1000 10 2 2 55 55 15 40 15 10 1 0 1 5 2 0 1.5 1.5 1 1.5 1 1.5 1 1.5 1 1 2 1 1 64 4.5 6 10 2.25 2.25 55 55 16.5 5 6 Clock high pulse width Clock low pulse width Access time form clock /RAS cycle time /CAS Latency = 3 /CAS Latency = 2 Operation Auto Refresh Max Min 5.5 1000 10 2.5 2.5 60 60 18 42 18 12 1 0 1 5 2 0 2.7 1.5 1 1.5 1 1.5 1 1.5 1 1 2 1 1 64 5.4 6 100K Max Min 6 1000 10 2.5 2.5 62 62 20 42 20 14 1 0 1 4 2 0 2.7 1.5 1 1.5 1 1.5 1 1.5 1 1.5 1 1 1 64 5.4 6 120K Max Min 7 1000 Max -5.5 -6 -7
ADS7608A4A
-7.5 Unit Note Min 7.5 1000 7.5 2.5 2.5 65 65 15 45 15 15 1 0 1 4 2 0 2.7 1.5 1 1.5 1 1.5 1 1.5 1 1.5 1 1 1 64 5.4 ns 5.4 ns 120K ns ns ns ns CLK CLK CLK CLK CLK CLK ns ns ns ns ns ns ns ns ns ns CLK CLK CLK ms 3 1 1 1 1 1 1 1 1 2 ns ns 1 1 ns Max
/RAS to /CAS delay /RAS active time /RAS precharge time /RAS to /RAS bank active delay /CAS to /CAS delay
100K 38.5 100K 16.5 11 1 0 1 5 2 0 2 1.5 1 1.5 1 1.5 1 1.5 1 1 2 1 1 64 -
Write command to data - in delay tWTL Data - in to precharge command Data - in active command DQM to data - out Hi-Z DQM to data - in mask Data - out hold time Data - input setup time Data - input hold time Address setup time Address hold time CKE setup time CKE hold time Command setup time Command hold time CLK to data output in low Z-time MRS to new command Power down exit time Self refresh exit time Refresh time tDPL tDAL tDQZ tDQM tOH tDS tDH tAS tAH tCKS tCKH tCS tCH tOLZ tMRD tPDE tSRE tREF
Note : 1. Assume tR / tF (input rise and fall time) is 1 ns. 2. Access times to be measured with input signals of 1v / ns edge rate. 3.A new command can be given tRRC after self refresh exit.
Rev 1 April, 2001
6
A-Data
Command Truth-Table
Command Mode Register Set No Operation Bank Active Read H Read with Auto Precharge Write Write with Auto Precharge Precharge All Bank H Precharge select Bank Burst Stop DQM Auto Refresh Entry Self Refresh Exit L H L H Entry Precharge Power down Exit L H L H Entry Clock Suspend Exit L H H L L V X V V X H X H X H X X H L L H H X H X H X X H X H X H X X H H H H H L L L H X L H X L L X L L X H H X X H L X V X X X L L H L X H X L H L L X X L H L H X CKEn-1 H H H CKEn X X L X L H L H H H H X /CS L H /RAS L X /CAS L X /WE L X X DQM X
ADS7608A4A
ADDR A10/AP OP code X RA L CA H CA L H H X L X X X
BA
V V
V X V
X
X
X
Rev 1 April, 2001
7
A-Data
Package Information
ADS7608A4A
SYMBOL A A1 A2 B c D HE E e L L1
MIN. 0.05 0.95 0.30 0.12 11.56 10.03 0.80 BSC 0.40
MILLIMETER NOM. 0.10 1.00 0.35 22.22 BSC 11.76 10.16 0.50 0.80 REF 0.71 REF -
MAX. 1.20 0.15 1.05 0.45 0.21 11.96 10.29 0.60
MIN. 0.002 0.037 0.012 0.005 0.460 0.390 0.031 0.016
INCH NOM. 0.004 0.039 0.014 0.875 BSC 0.463 0.400 0.020 0.031 REF 0.028 REF -
MAX. 0.047 0.006 0.041 0.018 0.008 0.470 0.410 0.024
S
0
8
0
8
400mil 54pin TSOP II Package
Rev 1 April, 2001
8

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